1. Technical Field
The invention relates in general to a semiconductor structure, and more particularly to a semiconductor structure with improved capacitance of bit lines.
2. Description of the Related Art
With the development of semiconductor technology, the demand for the memory device focuses on small size and larger memory capacity. For satisfying the requirement, a memory device having a high element density is need. Since the critical dimension of the memory device has been decreased to the ultimate in the art, designers develop a structure for improving the density of memory, using 3D stack memory device so as to increase the memory capacity and lower the size per cell. However, in the 3D stack structure, the bit lines connected to different stack blocks make the capacitance of each stack blocks in parallel, and the capacitances of the stack blocks summed up results in an increase of the capacitance of the bit lines, causing a delay for transmitting the bit signals.